SH7760 Datasheet, PDF (580/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

16.3.2 Free-Running Timer (CMTFRT)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
FRT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
31 to 0 FRT
Initial Value R/W
All 0
R
Description
Free-Running Timer
These bits indicate the current value of the
free-running timer (FRT).
16.3.3 Control Register (CMTCTL)
CMTCTL is a 32-bit readable/writable register that controls interrupts, makes settings for the
clocks, and selects the operating mode.
Bit:
Initial value:
R/W:
31
TE3
0
R/W
30
TE2
0
R/W
29
TE1
0
R/W
28 27 26 25 24 23 22
TE0 IOE3 IOE2 IOE1 IOE0 ICE3 ICE2
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
21 20 19 18
ICE1 ICE0 IEE3 IEE2
0
0
0
0
R/W R/W R/W R/W
17 16
IEE1 IEE0
0
0
R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CC3
CC2
CC1
CC0
SI3 SI2 SI1 SI0 OP3 OP2 OP1 OP0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name Initial Value R/W Description
31
TE3
0
30
TE2
0
29
TE1
0
28
TE0
0
R/W Timer Enable
R/W
Enables the counting of each of the 16-bit
counters. If these bits are inactive when operating
R/W
in timer mode or in counter mode, the counters
R/W ^{are reset to 0.}
In updown-counter mode, a counter for each pair
(counter 1 or counter 3) needs to be disabled
(TE1=0, TE3=0).
0: Counting disabled; counter will be reset to
H'000
1: Counter is incremented
Rev. 1.0, 02/03, page 530 of 1294