SH7760 Datasheet, PDF (519/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

12.3 Clock Operating Modes
Table 12.2 shows the relationship between the combinations of mode control pin (MD2 to MD0)
settings and clock operating modes.
Table 12.3 shows the FRQCR settings and internal clock frequencies.
Table 12.2 Clock Operating Modes
Clock
Operating
Mode
Pin Combination
MD2 MD1 MD0
PLL1
CPU
PLL2 Clock
Frequency
(vs. Input Clock)
Bus Peripheral
Clock Clock
FRQCR
Initial Value
0
0
0
0
On (×12) On 12
3
3
H'0E1A
1
0
0
1
On (×12) On 12
3/2
3/2
H'0E2C
2
0
1
0
On (×6) On 6
2
1
H'0E13
3
0
1
1
On (×12) On 12
4
2
H'0E13
4
1
0
0
On (×6) On 6
3
3/2
H'0E0A
5
1
0
1
On (×12) On 12
6
3
H'0E0A
6
1
1
0
Off (×6) Off 1
1/2
1/2
H'0808
Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode.
2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input
frequency (f_EX) and CKIO clock output (f_OP) in section 33.3.1, Clock and Control Signal
Timing.
Rev. 1.0, 02/03, page 469 of 1294