SH7760 Datasheet, PDF (506/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

11.6.8 Double Buffer Control for Audio Data
There are two types of transfer end interrupts.
• A0TXH, A0RXH, A1TXH, or A1RXH (half data transfer end interrupt)
An interrupt is generated when a half of the transfer size specified by DMAARXTCR or
DMAATXTCR is completed.*¹*²
• A0TXE, A0RXE, A1TXE, or A1RXE (all data transfer end interrupt)
An interrupt is generated when the whole transfer size specified by DMAARXTCR or
DMAATXTCR is completed.
Using half data transfer end and all data transfer end interrupts makes transfers for consecutive
audio data efficient since half of the transmit/receive buffer can be accessed by the CPU during a
transfer of the other half.*³
In addition, by enabling the auto reload function (TAR/RAR bit in DMAACR), it is not necessary
to re-specify the registers for the second transfer or later.
Notes: *1. When the transfer size specified in DMAARXTCR or DMAATXTCR is 4 bytes, a half
data transfer end interrupt is not generated.
*2. When the transfer size specified in DMAARXTCR or DMAATXTCR is 8n + 4 bytes
(n is an integer = 1 or greater) (transfer count is an odd number), a half data transfer
end interrupt is generated when n + 1 transfers are completed.
*3. The DMABRG for the HAC or SSI has FIFOs that stores a maximum of 64-byte data
that is pre-fetched on transmit. If a half of the transfer size of audio data is less than 64
bytes, the remaining data in the transmit/receive buffer may already be stored in the
FIFO when a half data transfer end interrupt is generated. When using the double
buffer control by a half data transfer end interrupt, configure the transmit/receive buffer
in synchronous DRAM having the size of 128 bytes or more.
11.6.9 HAC/SSI Endian Conversion Function
Data is transferred between the HAC or SSI and a transmit/receive buffer in 32-bit (longword)
units. When data less than 32 bits is transferred, the byte order of audio data in the
transmit/receive buffer in synchronous DRAM may differ from the DMA transfer order,
depending on the MD5 pin level which specifies the endian type.
(1) 8-Bit Data Transfer for SSI
When SSI handles the transfer of 8-bit (byte) audio data, data transfer starts from the least-
significant byte as shown in figure 11.36: first the left channel data is input to or output from
bits 7 to 0, secondly the right channel data is input to or output from bits 15 to 8, and then the
next left channel data is input to or output from bits 23 to 16. Selecting big endian mode (MD5
= 0) requires the conversion for alignment such that the least-significant byte is stored in the
Rev. 1.0, 02/03, page 456 of 1294