SH7760 Datasheet, PDF (738/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
8
DEL
0
• DWL = 010, 011, 100, 101 (data word length:
18, 20, 22 and 24 bits), PDTA = 0 (left
aligned)
The data bits which are used in SSIRDR or
SSITDR are the following:
Bits 31 to (32 – number of bits having data
word length specified by DWL).
If DWL = 011 then data word length is 20 bits
and bits 31 to 12 are used of either SSIRDR
or SSITDR. All other bits are ignored or
reserved.
• DWL = 010, 011, 100, 101 (data word length:
18, 20, 22 and 24 bits), PDTA = 1 (right
aligned)
The data bits which are used in SSIRDR or
SSITDR are the following:
Bits (number of bits having data word length
specified by DWL - 1) to 0.
If DWL = 011 then data word length is 20 bits
and bits 19 to 0 are used of either SSIRDR or
SSITDR. All other bits are ignored or
reserved.
• DWL = 110 (data word length: 32 bits), PDTA
ignored
All data bits in SSIRDR or SSITDR are used
on the audio serial bus.
R/W Serial Data Delay
0: 1 clock cycle delay between SSI_WS and
SSI_SDATA
1: No delay between SSI_WS and SSI_SDATA
This bit is ignored if CPEN = 1. A one-clock
cycle delay is not supported when the SSI
module is configured to be a slave transmitter
(SWSD = 0 and TRMD = 1). In this situation,
this bit should be set to 0.
Rev. 1.0, 02/03, page 688 of 1294