SH7760 Datasheet, PDF(280/1345 Page) Renesas Technology Corp – SuperHTM RISC engine

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SH7760 Datasheet, PDF (280/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

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â¢ Burst ROM interface

ï£§ Wait-cycle insertion can be controlled by program

ï£§ Burst transfer for the number of times specified by the register

ï£§ Connectable areas: 0, 5, 6

ï£§ Settable bus widths: 32, 16, 8

â¢ MPX interface

ï£§ Address/data multiplexing

ï£§ Peripheral LSI, which requires address/data multiplexing, can be connected

ï£§ Connectable areas: 0 to 6

ï£§ Settable bus width: 32

â¢ Byte control SRAM interface

ï£§ SRAM interface with byte control

ï£§ Connectable areas: 1, 4

ï£§ Settable bus widths: 32, 16

â¢ PCMCIA interface (valid only in little-endian mode)

ï£§ Wait-cycle insertion can be controlled by program

ï£§ Bus sizing function for I/O bus width

ï£§ Connectable areas: 5, 6

ï£§ Settable bus widths: 16, 8

â¢ Refresh counter can be used as interval timer

ï£§ Interrupt request generated by compare-match

ï£§ Interrupt request generated by refresh counter overflow

Rev. 1.0, 02/03, page 230 of 1294

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