SH7760 Datasheet, PDF (715/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

When changing the direction at the first transfer, retransmit command (Sr), the slave address and
the R/W signal are transmitted. In this case, the R/W signal is set to the direction opposite to the
first transfer direction.
S SLAVE ADDRESS R/W A DATA A/A Sr SLAVE ADDRESS R/W A DATA A/A P
(n bytes
Read or Write ^+ACK.)*
Read or Write
(n bytes
+ACK.)*
Sr = Restart condition
Direction of transfer
may change at this point
Note: * Transfer direction of data and acknowledge bits depend on R/W bits.
Figure 19.5 Combination Transfer Format of Master Transfer
19.4.7 10-Bit Address Format
Description is given below on the 10-bit address transfer format supported in the master mode.
This format has three transfer methods as the 7-bit address transfer format.
Figure 19.6 shows the data transfer format. The set value of the master address register is output in
one byte following the first transfer condition (S). The value set in transmit data register (ICTXD)
is transmitted as a slave address in the second byte. Data transfer on and after the third byte is
done in the same way as the 7-bit address data transmission.
11110XX
S SLAVE ADDRESS R/W A1 SLAVE ADDRESS A2 DATA A DATA A/A P
1st 7 bits of 1st byte
0 (write)
2nd byte
Data transferred
(n bytes + ACKNOWLEDGE)
Figure 19.6 10-Bit Address Data Transfer Format
Rev. 1.0, 02/03, page 665 of 1294