SH7760 Datasheet, PDF (860/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W
12
TCR12
0
R/W
11
TCR11
0
R/W
10-6 —
All 0
—
5
TCR5
0
R/W
4
TCR4
0
R/W
3
TCR3
0
—
2
TCR2
0
—
1
TCR1
0
—
0
TCR0
0
—
Description
TimeStamp Control for Transmission
Specifies if the Timestamp of each transmit
Mailbox is recorded at the point that the
corresponding CANTXPR bit is set or the
corresponding CANTXACK is set when a
transmission request is made.
0: Timestamp is recorded at the point that the
CANTXPR bit is set for message transmission.
1: Timestamp is recorded at the point that the
CANTXACK bit is set for message
transmission.
Timer Clear-Set- Control by CANTCMR
Specifies if the Timer is to be cleared and set to 0
when CANTCMR matches to CANTCNTR. Please
note that the CANTCMR is also capable to
generate an interrupt signal to the host CPU via
IRR15.
0: Timer is not cleared by CANTCMR.
1: Timer is cleared by CANTCMR.
Reserved
The write value should always be 0. The read
value cannot be guaranteed.
HCAN2 Timer Prescaler
This control fields allows the timer source clock (2
× Peripheral clock) to be divided before it is used
for the timer. The following relationship exists
between the source clock period and timer period:
000000: 1 × Source clock
000001: 2 × Source clock
000010: 4 × Source clock
000011: 6 × Source clock
000100: 8 × Source clock
:
111111: 126 × Source clock
22.5.17 Timer Compare Match Registers (CANTCMR)
The CANTCMR is a 16-bit read/write register capable of generating interrupt signals and clearing/
setting the timer value.
If a compare match occurs, an interrupt flag is set to Bit14 in CANIRR and this bit cannot be
prevented from being set in CANIRR except when the CANTCMR value is H'0000. Bit14 of
Rev. 1.0, 02/03, page 810 of 1294