SH7760 Datasheet, PDF (610/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
1
CKE1
0
0
CKE0
0
R/W Clock Enable 1, 0
R/W These bits select the SCIF clock source and
whether to enable or disable the clock output from
the SCIF_CLK pin. The CKE1 and CKE0 bits are
used together to specify whether the SCIF_CLK
pin functions as a serial clock output pin or a serial
clock input pin. Note however that the CKE0 bit
setting is valid only when an internal clock is
selected as the SCIF clock source (CKE1 = 0).
When an external clock is selected (CKE1 = 1),
the CKE0 bit setting is invalid. The CKE1 and
CKE0 bits must be set before determining the
SCIF's operating mode with SCSMR.
• Asynchronous mode
00: Internal clock/SCIF_CLK pin functions as port
01: Internal clock/SCIF_CLK pin functions as
clock output*¹
1X: External clock/SCIF_CLK pin functions as
clock input*²
• Synchronous mode
0X: Internal clock/SCIF_CLK pin functions as
synchronization clock output
1X: External clock/SCIF_CLK pin functions as
synchronization clock input
Notes: X: Don't care
*1. Outputs a clock with a frequency 16 times the bit rate.
*2. Inputs a clock with a frequency 16 times the bit rate.
17.3.7 Serial Status Register (SCFSR)
SCFSR is a 16-bit register that consists of status flags that indicate the operating status of the
SCIF.
SCFSR can be read from or written to by the CPU at all times. However, 1 cannot be written to
flags ER, TEND, TDFE, BRK, RDF, and DR. Also note that in order to clear these flags they
must be read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be
modified.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
- ER TEND TDFE BRK FER PER RDF DR
0
0
1
1
0
0
R R/W*¹ R/W*¹ R/W*¹ R/W*¹ R
0
0
0
R R/W*¹ R/W*¹
Rev. 1.0, 02/03, page 560 of 1294