SH7760 Datasheet, PDF (20/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Section 22 Hitachi Controller Area Network 2 (HCAN2) ................................757
22.1 Features............................................................................................................................. 757
22.2 Architecture ...................................................................................................................... 757
22.2.1 Block diagram...................................................................................................... 757
22.2.2 Block Function..................................................................................................... 759
22.3 Input/Output Pins .............................................................................................................. 760
22.4 Programming model – overview....................................................................................... 760
22.4.1 Memory map........................................................................................................ 760
22.4.2 Mail box............................................................................................................... 761
22.5 HCAN2 Control Registers ................................................................................................ 770
22.5.1 Master Control Register (CANMCR) .................................................................. 778
22.5.2 General Status Register (CANGSR) .................................................................... 784
22.5.3 Bit Configuration Registers 1 and 0 (CANBCR1, CANBCR0) .......................... 786
22.5.4 Interrupt Request Register (CANIRR)................................................................. 790
22.5.5 Interrupt Mask Register (CANIMR).................................................................... 795
22.5.6 Transmit Error Counter and Receive Error Counter (CANTECREC) ................. 796
22.5.7 Transmit Pending Request Registers 1 and 0 (CANTXPR1, CANTXPR0) ........ 797
22.5.8 Transmit Cancel Registers 1 and 0 (CANTXCR1, CANTXCR0) ....................... 799
22.5.9 Transmit Acknowledge Registers 0 and 1 (CANTXACK1, CANTXACK0)...... 801
22.5.10 Abort Acknowledge Registers 1 and 0 (CANABACK1, CANABACK0) .......... 802
22.5.11 Receive Data Frame Pending Registers 1 and 0 (CANRXPR1, CANRXPR0) ... 804
22.5.12 Remote Frame Request Pending Registers 1 and 0
(CANRFPR1, CANRFPR0) ................................................................................ 805
22.5.13 Mailbox Interrupt Mask Registers 1 and 0 (CANMBIMR1, CANMBIMR0) ..... 806
22.5.14 Unread Message Status Registers 1 and 0 (CANUMSR1, CANUMSR0)........... 807
22.5.15 Timer Counter Register (CANTCNTR)............................................................... 808
22.5.16 Timer Control Register (CANTCR) .................................................................... 809
22.5.17 Timer Compare Match Registers (CANTCMR).................................................. 810
22.6 Operation .......................................................................................................................... 812
22.6.1 Test Mode Settings .............................................................................................. 812
22.6.2 HCAN2 Settings .................................................................................................. 813
22.6.3 Message Transmission Sequence......................................................................... 814
22.6.4 Message Reception Sequence .............................................................................. 817
22.6.5 Reconfiguration of Mailbox................................................................................. 818
22.6.6 Standby Mode ...................................................................................................... 821
Section 23 Hitachi Serial Protocol Interface (HSPI).........................................823
23.1 Features............................................................................................................................. 823
23.2 Input/Output Pins .............................................................................................................. 824
23.3 Register Descriptions ........................................................................................................ 825
23.3.1 Control Register (SPCR)...................................................................................... 826
Rev. 1.0, 02/03, page xviii of xlviii