SH7760 Datasheet, PDF (710/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
31 to 3 
Initial Value R/W
All 0
R
2
TEIE
0
R/W
1
RXIE
0
R/W
0
TXIE
0
R/W
Description
Reserved.
These bits are always read as 0, and the write
value should always be 0.
Transmit End Interrupt Enable
Enables or disables the generation of the transmit
end interrupt (TEI) when the TEND flag of ICFSR
is set to 1.
0: The transmit end interrupt (TEI) is disabled
1: The transmit end interrupt (TEI) is enabled
Receive Interrupt Enable
Enables or disables the generation of the receive
data full interrupt (RXI) when the RDF flag of
ICFSR is set to 1.
0: The receive data full interrupt (RXI) is disabled
1: The receive data full interrupt (RXI) is enabled
Transmit Interrupt Enable
Enables or disables the generation of the transmit
FIFO data empty interrupt (TXI) when serial
transmit data is transferred from ICTXD to the
shift register, the byte count in ICTXD is equal to
or smaller than the transmit trigger byte count,
and the TDFE flag of ICFSR is set to 1.
0: The transmit FIFO data empty interrupt (TXI) is
disabled
1: The transmit FIFO data empty interrupt (TXI) is
enabled
19.3.14 Receive FIFO Data Count Register (ICRFDR)
ICRFDR is a 32-bit register that indicates the byte count in ICRXD. The lower 5 bits indicate the
number of receive bytes in ICRXD. ICRFDR can always be read by the CPU. H'0000 0000
indicates that ICRXD contains no receive data, while H'0000 0010 indicates that it is full of
receive data.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
R4 R3 R2 R1 R0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Rev. 1.0, 02/03, page 660 of 1294