SH7760 Datasheet, PDF (970/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

26.3.5 Command Registers 0 to 5 (CMDR0 to CMDR5)
The CMDR registers are six 8-bit registers. A command is written to CMDR as shown in table
26.4, and the command is transmitted when the START bit in CMDSTRT is set to 1.
Table 26.4 CMDR Configuration
Register
CMDR0
CMDR1 to
CMDR4
CMDR5
Contents
Start bit, Host bit, and
command index
Command argument
CRC and End bit
Operation
Write command indexes.
Clear the Start bit to 0 and set the Host bit to 1.
Write command arguments.
Setting of CRC is unnecessary (automatic calculation).
End bit is fixed to 1 and its setting is unnecessary.
• CMDR0
Bit: 7
6
5
4
3
2
1
0
Start Host
INDEX
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7
6
5 to 0
Bit Name
Start
Host
INDEX
Initial
Value
0
0
All 0
R/W Description
R/W Start bit (This bit should be cleared to 0)
R/W Transmission bit (This bit should be set to 1)
R/W Command indexes
• CMDR1 to CMDR4
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7 to 0
Bit
Name
—
Initial
Value
All 0
R/W Description
R/W Command arguments
See specifications for the MMC card.
Rev. 1.0, 02/03, page 920 of 1294