SH7760 Datasheet, PDF (11/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Section 8 Exceptions......................................................................................... 165
8.1 Exception Handling Functions..........................................................................................165
8.1.1 Exception Handling Flow ....................................................................................165
8.1.2 Exception Handling Vector Addresses ................................................................166
8.2 Exception Types and Priorities .........................................................................................167
8.3 Exception Flow .................................................................................................................171
8.3.1 Exception Flow ....................................................................................................171
8.3.2 Exception Source Acceptance..............................................................................172
8.3.3 Exception Requests and BL Bit ...........................................................................173
8.3.4 Return from Exception Handling .........................................................................173
8.4 Register Descriptions ........................................................................................................174
8.4.1 Exception Event Register (EXPEVT) ..................................................................175
8.4.2 Interrupt Event Register (INTEVT) .....................................................................175
8.4.3 TRAPA Exception Register (TRA) .....................................................................176
8.5 Operation...........................................................................................................................177
8.5.1 Resets ...................................................................................................................177
8.5.2 General Exceptions ..............................................................................................182
8.5.3 Interrupts..............................................................................................................196
8.5.4 Priority Order with Multiple Exceptions..............................................................200
8.6 Usage Notes ......................................................................................................................201
8.7 Restrictions .......................................................................................................................202
8.7.1 Restrictions on First Instruction in Exception Handling Routine ........................202
Section 9 Interrupt Controller (INTC) .............................................................. 203
9.1 Features .............................................................................................................................203
9.2 Input/Output Pins ..............................................................................................................205
9.3 Register Descriptions ........................................................................................................205
9.3.1 Interrupt Priority Level Setting Registers A to D (IPRA to IPRD)......................207
9.3.2 Interrupt Priority Level Setting Registers 00 to 0C (INTPRI00 to INTPRI0C)...208
9.3.3 Interrupt Control Register (ICR)..........................................................................209
9.3.4 Interrupt Source Registers 00, 04 (INTREQ00, INTREQ04) ..............................211
9.3.5 Interrupt Mask Registers 00, 04 (INTMSK00, INTMSK04) ...............................213
9.3.6 Interrupt Mask Clear Registers 00, 04 (INTMSKCLR00, INTMSKCLR04) ......216
9.4 Interrupt Sources ...............................................................................................................217
9.4.1 NMI Interrupt.......................................................................................................217
9.4.2 IRQ Interrupts ......................................................................................................217
9.4.3 IRL Interrupts.......................................................................................................217
9.4.4 Peripheral Module Interrupts ...............................................................................219
9.4.5 Interrupt Exception Handling and Priority...........................................................220
9.5 Operation...........................................................................................................................225
9.5.1 Interrupt Operation Sequence ..............................................................................225
9.5.2 Multiple Interrupts ...............................................................................................227
Rev. 1.0, 02/03, page ix of xlviii