SH7760 Datasheet, PDF (158/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(6) Single Virtual Memory Mode and Multiple Virtual Memory Mode
There are two virtual memory systems, single virtual memory and multiple virtual memory, either
of which can be selected with the SV bit in MMUCR. In the single virtual memory system, a
number of processes run simultaneously, using virtual address space on an exclusive basis, and the
physical address corresponding to a particular virtual address is uniquely determined. In the
multiple virtual memory system, a number of processes run while sharing the virtual address
space, and particular virtual addresses may be translated into different physical addresses
depending on the process. The only difference between the single virtual memory and multiple
virtual memory systems in terms of operation is in the TLB address comparison method (see
section 6.3.3, Address Translation Method).
(7) Address Space Identifier (ASID)
In multiple virtual memory mode, an 8-bit address space identifier (ASID) is used to distinguish
between multiple processes running simultaneously while sharing the virtual address space.
Software can set the 8-bit ASID of the currently executing process in PTEH in the MMU. The
TLB does not have to be purged when processes are switched by means of ASID.
In single virtual memory mode, ASID is used to provide memory protection for multiple processes
running simultaneously while using the virtual address space on an exclusive basis.
Note: Two or more entries with the same virtual page number (VPN) but different ASID must
not be set in the TLB simultaneously as a single virtual memory mode setting.
6.2 Register Descriptions
The following registers are related to MMU processing. For details on the addresses of these
registers and the state of registers in each operating mode, see section 32, List of Registers.
Table 6.1 Register Configuration (1)
Register Name
Abbrev.
Page table entry high register
PTEH
Page table entry low register
PTEL
Page table entry assistance register PTEA
Translation table base register
TTB
TLB exception address register
TEA
MMU control register
MMUCR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P4 Address
H’FF00 0000
H’FF00 0004
H’FF00 0034
H’FF00 0008
H’FF00 000C
H’FF00 0010
Area 7 Address Size
H’1F00 0000 32
H’1F00 0004 32
H’1F00 0034 32
H’1F00 0008 32
H’1F00 000C 32
H’1F00 0010 32
Sync
Clock
Ick
Ick
Ick
Ick
Ick
Ick
Rev. 1.0, 02/03, page 108 of 1294