SH7760 Datasheet, PDF (461/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Transfer request
Channel
1. Issued for channels 0 ^waiting
and 3
3. Issued for channel 1
3
DMAC operation
2. Start of channel 0
transfer
Channel priority order
0>1>2>3>4>5>6>7
Change of
priority order
1, 3
4. End of channel 0
transfer
1>2>3>4>5>6>7>0
5. Start of channel 1
transfer
Change of
priority order
3
6. End of channel 1
2>3>4>5>6>7>0>1
transfer
None
7. Start of channel 3
transfer
8. End of channel 3
transfer
Change of
priority order
4>5>6>7>0>1>2>3
Figure 11.5 Example of Changes in Priority Order in Round Robin Mode
11.4.4 Types of DMA Transfer
The DMAC supports the types of transfer shown in table 11.7. It can operate in single address
mode, in which either the transfer source or the transfer destination is accessed using the
acknowledge signal, or in dual address mode, in which both the transfer source and transfer
destination addresses are output. The actual transfer operation timing depends on the bus mode,
which can be either burst mode or cycle steal mode.
Rev. 1.0, 02/03, page 411 of 1294