SH7760 Datasheet, PDF (720/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

1. Check that the MIE bit of ICMCR is 0.
2. Check that the SIE bit of ICSCR is 0.
3. Monitor the status of the FSCL and FSDA bits of ICMCR to check that FSCL is 1 and FSDA
is 0. (Determine the timing for monitoring according to the SCL frequency to be used). When
the MIE and SIE bits are 1, check that communications are not in progress and clear these bits
to 0.
19.5 FIFO Mode Operation
In FIFO mode, the 16-stage FIFO buffer can be used. Registers related to the FIFO mode are
ICFCR, ICFSR, ICFIER, ICRFDR, and ICTFDR. For details, refer to the description of these
registers.
In FIFO mode, interrupt overhead can be reduced since transfer is performed in units of bytes
specified by ICFCR.
19.5.1 Master Transmitter Operation (FIFO Buffer Mode)
1. The MDE bit and the MAT bit are set to 1 at the same timing, as in single buffer mode. At this
time, the ESG bit should be cleared to 0. The master device holds SCL low level until the
MDE bit is cleared to 0 in order to suspend data transfer.
2. The FSB should be set to 1 when the transmit end flag (TEND) is set to 1. For example, to
transmit 3-byte data, write the 3 bytes to the FIFO and transmit the data. Then set the FSB bit
to 1 after the transmit completion is notified by an TEND interrupt.
19.5.2 Master Receiver Operation (FIFO Buffer Mode)
1. Clear the ESG bit to 0 when the RDF bit is set to 1 by receiving data for the byte count
specified by the register.
2. The receive byte count specified by the RTRG bits in ICFCR can be selected from 1 to 16.
3. When the receive byte count reaches the specified count, an RDF interrupt is generated (RXIE
= 1) and receive operation is stopped. The ACK signal is automatically returned until the RDF
bit is set to 1.
4. Read all the receive data in the receive FIFO by the CPU when the RDF interrupt occurs.
(Dummy-reading or reading before an RDF interrupt generation is not allowed.) However, if
issuing a STOP condition is needed, carry out step 6.
5. To resume receive operations, read all the receive data in the receive FIFO with FSB = 0 and
then clear the RDF flag in ICFSR to 0. (Modify the RTRG bits before clearing the RDF flag,
if necessary.)
6. In order to issue a STOP condition, set the FSB bit to 1 and wait at least on bit period. Then
read all the receive data in the receive FIFO and clear the RDF flag to 0. (The FSB bit must be
set only in this timing).
Rev. 1.0, 02/03, page 670 of 1294