SH7760 Datasheet, PDF (186/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

6.6.6 UTLB Data Array 2
UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and SA and TC to be written to data array 2 are specified in the data
field.
In the address field, bits [31:23] have the value H’F78 indicating UTLB data array 2 and the entry
is specified by bits [13:8].
In the data field, bit [3] indicates TC and bits [2:0] indicate SA.
The following two kinds of operation can be used on UTLB data array 2:
1. UTLB data array 2 read
SA and TC are read into the data field from the UTLB entry corresponding to the entry set in
the address field.
2. UTLB data array 2 write
SA and TC specified in the data field are written to the UTLB entry corresponding to the entry
set in the address field.
31
23 22
14 13
87
0
Address field _{1 1 1 1 0 1 1 1 1}
E
31
Data field
432 0
SA[2:0]
TC: Timing control bit SA[2:0]: Space attribute bits
TC
E: Entry
: Reserved bits (write value should be 0,
and read value is undefined )
Figure 6.17 Memory-Mapped UTLB Data Array 2
Rev. 1.0, 02/03, page 136 of 1294