SH7760 Datasheet, PDF (324/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W
Description
2
A6TEH2 0
1
A6TEH1 0
0
A6TEH0 0
R/W OE/WE Negation-Address Delay A6
R/W
These bits set the address hold delay time after OE/WE
R/W
negation in the connected PCMCIA interface. The
setting of these bits is selected when the PCMCIA
interface access TC bit is 1.
Wait cycles to be Inserted
000: 0
001: 1
010: 2
011: 3
100: 6
101: 9
110: 12
111: 15
10.5.11 Synchronous DRAM Mode Register (SDMR)
SDMR is a 16-bit write-only virtual register that is written to via the synchronous DRAM address
bus, and sets the mode of the area 2 and area 3 synchronous DRAM.
Settings for the SDMR register must be made before accessing synchronous DRAM.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: W W W W W W W W W W W W
WWW
W
Since the address bus, not the data bus, is used to write to the synchronous DRAM mode register,
if the value to be set is "X" and the SDMR register address is "Y", value "X" is written to the
synchronous DRAM mode register by performing a write to address X + Y. When the
synchronous DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to
A2 of this LSI, and A1 of the synchronous DRAM is connected to A3 of this LSI, the value
actually written to the synchronous DRAM is the value of "X" shifted 2 bits to the right.
For example, to write H'0230 to SDMR in area 2, arbitrary data is written to address H'FF90 0000
(address "Y") + H'08C0 (value "X") (= H'FF90 08C0). As a result, H'0230 is written to the SDMR
register. The range of value "X" is H'0000 to H'0FFC.
Rev. 1.0, 02/03, page 274 of 1294