SH7760 Datasheet, PDF (493/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

2. End of transfer with DMAOR.NMIF = 1
If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended on
all channels in accordance with the procedures in 1, 2, 3, and 4 in section 11.4.6, and the bus is
passed to the CPU. Therefore, when NMIF is set to 1, the SAR, DAR, and DMATCR values
indicate the addresses for the DMA transfer to be performed next and the remaining number of
transfers. The TE bit is not set to 1 in this case. To resume DMA transfer after NMI interrupt
handling is completed, first re-specify DMARSRA/DMARSRB even when there is no
resource change. After that read NMIF = 1 and then write NMIF = 0. Acceptance of external
requests is suspended while the NMIF bit is set to 1, so a DMA transfer request must be
reissued when resuming transfer. Acceptance of on-chip peripheral module requests is also
suspended, so when resuming transfer, the DMA transfer request enable bit for the relevant on-
chip peripheral module must be cleared to 0 before the new setting is made. DMABRG must
be reset for DMABRG requests. See section 11.6.2, DMABRG Reset for the procedure.
3. End of transfer with DMAOR.DME = 0
If the DME bit in DMAOR is cleared to 0, DMA transfer is suspended on all channels in
accordance with the procedures in 1, 2, 3, and 4 in section 11.4.6, and the bus is passed to the
CPU. The TE bit is not set to 1 in this case. When the DME bit is cleared to 0, the SAR, DAR,
and DMATCR values indicate the addresses for the DMA transfer to be performed next and
the remaining number of transfers. When resuming transfer, set DME to 1. Operation will then
be resumed from the next transfer.
(3) Notes on Transfer End
When DMA transfer ends, requests may be retained in DMAC. Following are examples of
cancellation of requests retained in DMAC.
• External requests
See (2) External Request Mode, in section 11.4.2, DMA Transfer Requests.
• On-chip peripheral module requests
Retained requests may be processed if DMA transfer occurs. If DMARCR.REXn = 1 when
DMA transfer ends then external requests will be retained in DMAC. Examples of processing
are shown below.
1. After DMA transfer ends, set the corresponding resources in DMARSRA or DMARSRB to
H’00. (Write H’80.)
2. Read Bit REXn corresponding to the channel in DMARCR.
REXn = 0: The DMAC has not accepted (retained) a transfer request. Go to 9.
REXn = 1: The DMAC has accepted (retained) a transfer request. Go to 3.
3. Set the channel resources corresponding to DMARSRA, DMARSRB to H’7F. (Write H’FF.)
4. Specify external address space in the corresponding channel SARn (the lower 6 bits are 32-bit
boundary), and P4 address H’FE09 0020 in DARn.
5. Specify H’0000 0001 in DMATCRn of the corresponding channel.
Rev. 1.0, 02/03, page 443 of 1294