SH7760 Datasheet, PDF (1031/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

27.3.6 MFI External Interrupt Control Register (MFIEICR)
The MFIEICR is a 32-bit register that the on-chip CPU uses to issue interrupts an MFI-connected
external device.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
- EIC6 EIC5 EIC4 EIC3 EIC2 EIC1 EIC0 EIR
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 8
7
6
5
4
3
2
1
0
Bit
Initial
Name Value R/W Description

All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
EIC6 0
EIC5 0
EIC4 0
EIC3 0
EIC2 0
EIC1 0
EIC0 0
R/W External interrupt source
R/W Bits used to specify the interrupt source generated by
R/W the EIR. Both the MFI-connected external device and
R/W the on-chip CPU can write to these bits. Using these bits
R/W enables fast interrupt handling. These bits are
R/W completely under software control, and their values have
R/W no effect on the operation of the LSI.
EIR
0
R/W External interrupt request
While this bit is 1, the MFI-INT pin is asserted low and
interrupt request is issued to the external device from
this LSI.
Rev. 1.0, 02/03, page 981 of 1294