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| SH7760 Datasheet, PDF (405/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine | |||
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CKIO
A25âA0
CSn
RD/WR
RD
D31âD0
(read)
WEn
T1
Tw
Twe
T2
BS
RDY
DACKn
(SA: IO â memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.59 Byte Control SRAM Basic Read Cycle
(One Internal Wait + One External Wait)
Rev. 1.0, 02/03, page 355 of 1294
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