SH7760 Datasheet, PDF (723/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(a) Execute processing of the last byte receive interrupt (MDR), i.e., extract the data and clear
MDR.
(b) Wait for a master device's event (the MST bit in the master status register).
(c) Reset the MST bit to 0.
19.6.3 Master Transmitter—Restart—Master Receiver (Single Buffer Mode)
In order to set up the master interface for transmitting data packets to the I²C bus, issuing a restart,
and reading data back from the slave, take the following steps.
(1) Load the clock control register:
(a) Set SCL clock generation divider (SCGD) 01h.
(SCL frequency of 400 kHz)
(b) Set clock division ratio (CDF) is set to 2h.
(Off-chip clock(sysclockfreq): 33MHz, on-chip clock (clockfreq): 11 MHz)
(2) Load the master control register and address:
(a) Set address of slave being accessed to the master address register and the STM1 bit (write
mode: 0).
(b) Set the master control register to 89h.
(MDBS = 1, MIE = 1, and ESG = 1)
(3) Wait for the address to be output:
(a) Wait for master device’s events (interrupts by the MAT bit and the MDE bit in the master
status register).
(b) Set address of slave being accessed to the master address register and the STM1 bit (read
mode: 1).
If the enable start generation bit in the master control register is still set to 1, the master
will issue a restart at the end of the byte transmission. Since the new address has been
loaded as described above, the bus direction will be turned around.
(c) Reset the MAT bit to 0.
(4) Wait for the address to be output:
(a) Wait for master device’s events (interrupts by the MAT bit and the MDR bit of the master
status register).
(b) Set the master control register to 88h.
(The master device holds the SCL low level in order to suspend the data reception until the
MDR bit is cleared to 0).
(c) Reset the MAT bit to 0.
(5) Monitor the progress of data byte reception:
(a) Wait for a master event (the MDR bit in the master status register).
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