SH7760 Datasheet, PDF (413/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 11.2 shows a block diagram of the DMABRG.
For data transfer in DMABRG mode between synchronous DRAM and the LCDC, HAC, SSI, or
USB, the DMABRG performs a high-speed data transfer via the DMABRG internal FIFO (32-bit
16-stage) using DMAC channel 0. The DMABRG transfers a maximum of 32-byte data in a single
transfer.
On-chip peripheral
module
HAC(0)/
SSI(0)
HAC(0)/SSI(0)
bridge bus
HAC(1)/
SSI(1)
HAC(1)/SSI(1)
bridge bus
DMAC
DMABRG
16-stage 32-bit FIFO
16-stage 32-bit FIFO
16-stage 32-bit FIFO
16-stage 32-bit FIFO
USB
USB
bridge bus
16-stage 32-bit FIFO
16-stage 32-bit FIFO
LCDC
LCDC
bridge bus
16-stage 32-bit FIFO
DMABRGCR
DMAATXSAR0
DMAARXDAR0
DMAATXTCR0
DMAARXTCR0
DMAACR0
DMAATXTCNT0
DMAARXTCNT0
DMAUSAR
DMAUDAR
Transfer request
priority control
DMAATXSAR1
DMAARXDAR1
DMAATXTCR1
DMAARXTCR1
DMAACR1
DMAATXTCNT1
DMAARXTCNT1
DMAURWSZ
DMAUCR
Bus state
controller
External bus
Synchronous DRAM
Figure 11.2 DMABRG Block Diagram
Rev. 1.0, 02/03, page 363 of 1294