SH7760 Datasheet, PDF (496/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 11.11 (2) Conditions for Transfer between External Memory and External Device
with DACK, and Corresponding Register Settings
Transfer Condition
Register
Setting
Transfer source: external memory
SAR1
H'0C00 0000
Transfer destination: external device with DACK DAR1
(Accessed by DACK)
Number of transfers: 32
Transfer source address: decremented
DMATCR1
CHCR1
H'0000 0020
H'0000 22A5*¹
(H'0000 22AD*² when writing)
Transfer destination address: (setting invalid)
Transfer request source: external pin (DREQ1)
edge detection
DMARCR
H'0003 0040
Bus mode: burst
DMARSRA
H'0011 0000
(H'0091 0000*³ when writing)
Transfer unit: word
Request reception priority: round robin
No interrupt request at end of transfer
DMABRG mode
DMAOR
H'0000 C201
Channel priority order: 2 > 0 > 1 > 3 > 4 > 5 > 6 > 7
Notes: 1. When DREQ0 to DREQ3 are specified as DMA transfer request sources in DMABRG
mode, any channels can accept the requests (a limitation on the use of channels in
DMABRG mode is only for a DMABRG request).
2. Always write 1 to the CHSET bit when modifying the CHCRn value in DMABRG mode.
3. Always write 1 to the CHnWEN bit of the corresponding channel when modifying the
DMARSRA or DMARSRB value.
Rev. 1.0, 02/03, page 446 of 1294