SH7760 Datasheet, PDF (467/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 11.8 Relationship between DMA Transfer Type, Request Mode, and Bus Mode
Address
Mode
Type of Transfer
Request Bus
Mode
Mode
Single
External device with DACK and
external memory
External B/C
Dual
External device with DACK and
memory-mapped external device
External memory and external memory
External memory and
memory-mapped external device
Memory-mapped external device and
memory-mapped external device
External memory and
on-chip peripheral module
Memory-mapped external device and
on-chip peripheral module
External B/C
Internal*¹,
external*⁵
Internal*¹,
external*⁵
Internal*¹,
external*⁵
Internal*²
B/C
B/C
B/C
B/C*³
Internal*² B/C*³
Legend
32B:
32-byte burst transfer
B:
Burst
C:
Cycle steal
External: External request
Internal: Auto-request and on-chip peripheral module request
Transfer Size
(Bits)
8/16/32/64/32B
8/16/32/64/32B
8/16/32/64/32B
8/16/32/64/32B
8/16/32/64/32B
8/16/32/64*⁴
8/16/32/64*⁴
Notes: *1. External request, auto-request, or on-chip peripheral module request possible.
*2. Auto-request or on-chip peripheral module request possible.
*3. Only cycle steal mode when the transfer request source is an on-chip peripheral
module other than the DMABRG.
*4. Access size permitted for the on-chip peripheral module register that is the transfer
source or transfer destination.
*5. See tables 11.9 (1) and 11.9 (2) for the transfer sources and transfer destinations in
DMA transfer by means of an external request.
• External Request 2-Channel Mode
Table 11.9 (1) shows the memory interfaces that can be specified for the transfer source and
transfer destination in DMA transfer initiated by an external request in external request 2-
channel mode supported by this LSI.
Rev. 1.0, 02/03, page 417 of 1294