SH7760 Datasheet, PDF (703/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
31 to 8 
Initial Value R/W
All 0
R
7 to 2 SCGD
All 0
R/W
1, 0
CDF
All 0
R/W
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
SCL Clock Generation Divider
In master mode operation, the SCL clock is
generated from the internal clock frequency using
the SCGD value as the division ratio. In slave
mode operation, if SCL is held low to stall the bus
by data overflow, this clock is also generated from
the internal clock. Accordingly, SCGD must be
programmed for master and slave operating
modes. The formula expressing the relationship is:
Equation 2 SCL rate calculation
SCL freq = IICck / (20 + SCGD * 8)
Recommended settings for CDF and SCGD for
various CPU rates and the two I²C bus speeds are
given in table 19.3.
Clock Division Factor
The internal clocks for most of the blocks in the I²C
bus interface module are divided from peripheral
bus clock. The internal I²C clock is generated from
the peripheral clock using the value of CDF as the
division ratio:
Equation 1 I²C internal clock frequency calculation
IICck = Pck / (1 + CDF)
The minimum setup and hold times on the SMA
line relative to the SCL line on the bus should be
met.
The clock frequency is to ensure that the glitch
filtering will operate with glitches of up to 50 ns (as
described in the fast mode I²C specifications).
Note: CDF must be set to a value that the clock
frequency (IICck) is less than 20 MHz.
Table 19.3 CDF and SCGD Recommended Values
Pck
33 MHz
Error
25 MHz
Error
CDF
3
2
100 kHz
SCGD
8
–1.79%
8
0.97%
400 kHz
CDF
SCGD
2
1
–1.79%
0
6
–8.08824%
Rev. 1.0, 02/03, page 653 of 1294