SH7760 Datasheet, PDF (156/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

256
P0 area
Cacheable
Address translation possible
External 256
memory space
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
U0 area
Cacheable
Address translation possible
P1 area
Cacheable
Address translation not possible
P2 area
Non-cacheable
Address translation not possible
P3 area
Cacheable
Address translation possible
P4 area
Non-cacheable
Address translation not possible
Privileged mode
Address error
Store queue area
Address error
User mode
Figure 6.5 Virtual Address Space (AT = 1 in MMUCR)
P0, P3, and U0 Areas: The P0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF), P3 area,
and U0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF) allow access using the cache and
address translation using the TLB. These areas can be mapped onto any external memory space in
1-, 4-, or 64-kbyte, or 1-Mbyte page units. When CCR is in the cache enabled state and the TLB
cacheability bit (C bit) is 1, accesses can be performed using the cache. In write accesses to the
cache, switching between the copy-back method and the write-through method is indicated by the
TLB write-through bit (WT bit), and is specified in page units.
Only when the P0, P3, and U0 areas are mapped onto external memory space by means of the
TLB, addresses H'1C00 0000 to H'1FFF FFFF of area 7 in the external memory space are
allocated to the control register area. This enables control registers to be accessed from the U0
area even in user mode. In this case, the C bit for the corresponding page must be cleared to 0.
P1, P2, and P4 Areas: Address translation using the TLB cannot be performed for the P1, P2, or
P4 area (except for the store queue area). Accesses to these areas are the same as for the physical
address space. The store queue area can be mapped onto any external memory space by the MMU.
However, operation in the case of an exception differs from that for normal P0, U0, and P3 areas.
For details, see section 7.7, Store Queues.
Rev. 1.0, 02/03, page 106 of 1294