SH7760 Datasheet, PDF (1016/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CPU
Start transfer-ready
Clear FIFO
Set DMAC-related
conditions
Set DMACR
(DMA enable on)
MMCIF
DMAC
FIFO data amount
Start transfer
No
DMA enable?
Yes
DMA request
No
assert condition?
Yes
DMA request assert
Assert condition
Transfer-end
interrupt processing
DMA transfer-end
interrupt processing
No
Transfer end?
Yes
DMAC initiation
Read from FIFO
No
DMA transfer end?
Yes
End
Figure 26.22 Example of Read Sequence Flow
Rev. 1.0, 02/03, page 966 of 1294