SH7760 Datasheet, PDF (205/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

7.5.4 OC Data Array
The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The entry to be accessed is specified in the address field, and the longword
data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the entry is
specified by bits [13:5]. The OIX and ORA bits in CCR have no effect on this entry specification.
Address field bits [4:2] are used for the longword data specification in the entry. As only longword
access is used, 0 should be specified for address field bits [1:0].
The data field is used for the longword data specification.
The following two kinds of operation can be used on the OC data array:
1. OC data array read
Longword data is read into the data field from the data specified by the longword specification
bits in the address field in the OC entry corresponding to the entry set in the address field.
2. OC data array write
The longword data specified in the data field is written for the data specified by the longword
specification bits in the address field in the OC entry corresponding the entry set in the address
field. This write does not set the U bit to 1 on the address array side.
31
24 23
Address field _{1 1 1 1 0 1 0 1}
14 13
Entry
54 210
L
31
0
Data field
Longword data
L : Longword specification bits
: Reserved bits (write value should be 0, and read value is undefined )
Figure 7.8 Memory-Mapped OC Data Array
Rev. 1.0, 02/03, page 155 of 1294