SH7760 Datasheet, PDF (18/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

19.3.8 Master Address Register (ICMAR) ..................................................................... 652
19.3.9 Clock Control Register (ICCCR) ......................................................................... 652
19.3.10 Receive/Transmit Data Registers (ICRXD/ICTXD)............................................ 654
19.3.11 FIFO Control Register (ICFCR) .......................................................................... 655
19.3.12 FIFO Status Register (ICFSR) ............................................................................. 657
19.3.13 FIFO Interrupt Enable Register (ICFIER) ........................................................... 659
19.3.14 Receive FIFO Data Count Register (ICRFDR) ................................................... 660
19.3.15 Transmit FIFO Data Count Register (ICTFDR) .................................................. 661
19.4 Operation .......................................................................................................................... 661
19.4.1 Data and Clock Filters ......................................................................................... 661
19.4.2 Clock Generator................................................................................................... 661
19.4.3 Master and Slave Interfaces ................................................................................. 661
19.4.4 Software Status Interlocking................................................................................ 662
19.4.5 I²C Bus Data Format ............................................................................................ 663
19.4.6 7-Bit Address Format........................................................................................... 664
19.4.7 10-Bit Address Format......................................................................................... 665
19.4.8 Master Transmit Operation (Single Buffer Mode)............................................... 666
19.4.9 Master Receiver Operation (Single Buffer Mode)............................................... 668
19.4.10 Standby Mode ...................................................................................................... 669
19.5 FIFO Mode Operation....................................................................................................... 670
19.5.1 Master Transmitter Operation (FIFO Buffer Mode) ............................................ 670
19.5.2 Master Receiver Operation (FIFO Buffer Mode) ................................................ 670
19.6 Programming Examples.................................................................................................... 671
19.6.1 Master Transmitter (Single Buffer Mode) ........................................................... 671
19.6.2 Master Receiver (Single Buffer Mode)................................................................ 672
19.6.3 Master Transmitter—Restart—Master Receiver (Single Buffer Mode) .............. 673
19.6.4 Master Transmitter (FIFO Buffer Mode)............................................................. 674
19.6.5 Master Receiver (FIFO Buffer Mode) ................................................................. 674
19.7 Usage Notes ...................................................................................................................... 675
19.7.1 Restriction 1......................................................................................................... 675
19.7.2 Restriction 2......................................................................................................... 678
Section 20 Serial Sound Interface (SSI) Module ..............................................681
20.1 Features............................................................................................................................. 681
20.2 Input/Output Pins .............................................................................................................. 682
20.3 Register Descriptions ........................................................................................................ 683
20.3.1 Control Register (SSICR) .................................................................................... 684
20.3.2 Status Register (SSISR) ....................................................................................... 690
20.3.3 Transmit Data Register (SSITDR) ....................................................................... 695
20.3.4 Receive Data Register (SSIRDR) ........................................................................ 695
20.4 Operation .......................................................................................................................... 696
20.4.1 Bus Format........................................................................................................... 696
Rev. 1.0, 02/03, page xvi of xlviii