SH7760 Datasheet, PDF (1153/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

31.3.2 Explanation of Terms Instruction Intervals
In this section, “1 (2, 3 …) instruction(s) after…”, as a measure of the distance between two
instructions, is defined as follows. A branch is counted as an interval of two instructions.
(1) Example of sequence of instructions with no branch:
100 Instruction A (0 instructions after instruction A)
102 Instruction B (1 instruction after instruction A)
104 Instruction C (2 instructions after instruction A)
106 Instruction D (3 instructions after instruction A)
(2) Example of sequence of instructions with a branch (however, the example of a sequence
of instructions with no branch should be applied when the branch destination of a
delayed branch instruction is the instruction itself + 4):
100 Instruction A: BT/S L200 (0 instructions after instruction A)
102 Instruction B (1 instruction after instruction A, 0 instructions after instruction B)
L200 200 Instruction C (3 instructions after instruction A, 2 instructions after instruction B)
202 Instruction D (4 instructions after instruction A, 3 instructions after instruction B)
31.3.3 User Break Operation Sequence
The sequence of operations from setting of break conditions to user break exception handling is
described below.
1. Specify pre- or post-execution break in the case of an instruction access, inclusion or exclusion
of the data bus value in the break conditions in the case of an operand access, and use of
independent or sequential channel A and B break conditions in BRCR. Set the break addresses
in BARA and BARB, set the ASIDs corresponding to the break space in BASRA and BASRB,
and set the address and ASID masking methods in BAMRA and BAMRB. If the data bus
value is to be included in the break conditions, also set the break data in BDRB and the data
mask in BDMRB.
2. Set the break bus conditions in BBRA and BBRB. If even one of the BBRA/BBRB instruction
access/operand access select (the ID bit) and read/write select groups (the RW bit) is set to
B'00, a user break interrupt will not be generated on the corresponding channel. Make the
BBRA and BBRB settings after all other break-related register settings have been completed.
If breaks are enabled with BBRA/BBRB while the break address, data, mask register, or the
break control register is in the initial state after a reset, a break may be generated inadvertently.
3. The operation when a break condition is satisfied depends on the BL bit in SR of the CPU.
When the BL bit is 0, exception handling is started and the condition match flag
(CMFA/CMFB) for the respective channel is set for the matched condition. When the BL bit is
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