SH7760 Datasheet, PDF (789/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
31 to 14 
All 0
R Reserved
These bits are always read as 0. Always write 0 to
this bit.
13 to 0 PS
All 0
R/W Periodic Start
After a hardware reset, this bit is cleared. Then, HCD
sets this bit to 1 during the HC initialization. The
value is calculated roughly as 10% subtracted from
the HcFmInterval value. When HcFmRemaining
reaches the specified value, processing of the
periodic lists will have priority over Control/Bulk
processing. HC will therefore start processing the
Interrupt list after completing the current Control or
Bulk transaction that is in progress.
21.3.18 Low Speed Threshold Register (HcLSThreshold)
HcLSThreshold stores an 11-bit LST value that is used by HC to determine whether or not to
authorize the transfer of the LS packet of up to 8 bytes, before EOF. HC and HCD cannot change
this value.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
LST
Initial value: 0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
R/W: R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name Initial Value R/W Description
31 to 12 
All 0
R Reserved
These bits are always read as 0. Always write 0 to
this bit.
11 to 0 LST
H’628
R/W LS Threshold
This field contains a value which is compared to the
FR bit prior to initiating a Low Speed transaction. The
transaction is started only if the value of the FR bit is
equivalent to or larger than that of this bit. HCD
calculates the value of this bit taking transmission
and setup overhead into consideration.
Rev. 1.0, 02/03, page 739 of 1294