SH7760 Datasheet, PDF (212/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

7.7.2 Writing to SQ
A write to the SQs can be performed using a store instruction for addresses H'E000 0000 to
H'E3FF FFFC in the P4 area. A longword or quadword access size can be used. The meanings of
the address bits are as follows:
[31:26]
[25:6]
[5]
: 111000
: Don't care
: 0/1
[4:2]
[1:0]
: LW specification
: 00
Store queue specification
Used for external memory transfer/access right
0: SQ0 specification
1: SQ1 specification
Specifies longword position in SQ0/SQ1
Fixed at 0
7.7.3 Transfer to External Memory
Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF).
Issuing a PREF instruction for addresses H'E000 0000 to H'E3FF FFFC in the P4 area starts a
transfer from the SQs to external memory. The transfer length is fixed at 32 bytes, and the start
address is always at a 32-byte boundary. While the contents of one SQ are being transferred to
external memory, the other SQ can be written to without a penalty cycle. However, writing to the
SQ involved in the transfer to external memory is kept waiting until the transfer is completed.
The external address bits [28:0] of the SQ transfer destination are specified as shown below,
according to whether the MMU is on or off.
• When MMU is on (AT = 1 in MMUCR)
The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer
destination external address in PPN. The ASID, V, SZ, SH, PR, and D bits have the same
meaning as for normal address translation, but the C and WT bits have no meaning with regard
to this page. Transfer to the PCMCIA interface area by means of the SQs is not allowed. When
a prefetch instruction is issued for the SQ area, address translation is performed and external
address bits [28:10] are generated in accordance with the SZ bit specification. For external
address bits [9:5], the address prior to address translation is generated in the same way as when
the MMU is off. External address bits [4:0] are fixed at 0. Transfer from the SQs to external
memory is performed to this address.
Rev. 1.0, 02/03, page 162 of 1294