SH7760 Datasheet, PDF (341/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

When area 6 is accessed while the SRAM interface is in use, the CS6 signal is asserted. the RD
signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. While
the PCMCIA interface is in use, the CE1B and CE2B signals, the RD signal, which can be
used as OE, the WE1, WE2, WE3, and WE0 signals, which can be used as WE, ICIORD,
ICIOWR, and REG, respectively, are asserted.
As regards the number of bus cycles, 0 to 15 wait cycles is selectable with bits A6W2 to
A6W0 in WCR2. In addition, any number of wait cycles can be inserted in each bus cycle by
the external wait pin (RDY).
When the burst ROM interface is in use, the number of bus cycles for burst transfer is selected
in the range of 2 to 9 according to the number of wait cycles.
The setup time of the address and CS signal with respect to the read/write strobe can be
specified by bit A6S0 in WCR3 within a range of 0 to 1 cycle. The data-hold time of the
address and CS signal with respect to the read/write strobe can be specified by bits A6H1 and
A6H0 within a range of 0 to 3 cycles.
The setup time of the address, CE1B, and CE2B signals with respect to the read/write strobe
can be specified by bits A6TED1 and A6TED0 in PCR within a range of 0 to 15 cycles. The
hold time of the address, CE1B, and CE2B signals can be specified by bits A6TEH1 and
A6TEH0 in PCR within a range of 0 to 15 cycles. The number of wait cycles can be specified
by bits A6PCW1 and A6PCW0 within a range of 0 to 50 cycles. The number of wait cycles
specified by PCR is added to the value specified by WCR2.
10.6.3 SRAM Interface
(1) Basic Timing
The strobe signals for the SRAM interface of this LSI are output primarily based on the SRAM
connection. Figure 10.6 shows the basic timing of SRAM interface. A no-wait normal access is
completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus
cycle. The CSn signal is asserted at the rising edge of the clock in the T1 state, and negated at
the rising edge of the clock after the T2 state. Therefore, there is no negation period in the case
of access at minimum pitch.
When reading, specifying an access size is not needed. The output addresses on the address
pins (A25 to A0) are correct, but since the access size is not specified, 32-bit data is always
output when a 32-bit device is in use, and 16-bit data is output when a 16-bit device is in use.
When writing, only the WEn signal corresponding to the byte to be written is asserted. For
details, see section 10.6.1, Endian/Access Size and Data Alignment.
Rev. 1.0, 02/03, page 291 of 1294