SH7760 Datasheet, PDF (320/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W
Description
9

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
8
SZ1
0
7
SZ0
0
R/W Memory Data Size
R/W
These bits specify the bus width of synchronous DRAM.
This setting has priority over the BCR2 register setting.
Synchronous DRAM
00: Setting prohibited
01: Setting prohibited
10: Setting prohibited
11: 32 bits
6
AMXEXT 0
5
AMX2 0
4
AMX1 0
3
AMX0 0
R/W Address Multiplexing
R/W
These bits specify address multiplexing for synchronous
R/W
DRAM. For details, refer to appendix D, Address
R/W
Multiplexing for Synchronous DRAM.
0000:
1000:
0001:
1001:
0010:
0011:
0100:
0101:
0110:
1110:
0111
Synchronous DRAM structure
example
(512k × 16 bits × 2) × 2
(512k × 16 bits × 2) × 2
(1M × 8 bits × 2) × 4
(1M × 8 bits × 2) × 4
(1M × 16 bits × 4) × 2
(2M × 8 bits × 4) × 4
(512k × 32 bits × 4) × 1
(1M × 32 bits × 2) × 1
(4M × 4 bits × 4) × 8
(4M × 16 bits × 4) × 2
(256k × 32 bits × 2) × 1
Bank
a[21]*³
a[20]*³
a[22]*³
a[21]*³
a[23:22]*³
a[24:23]*³
a[22:21]*³
a[22]*³
a[25:24]*³
a[25:24]*³
a[20]*³
Other settings are prohibited.
2
RFSH 0
R/W Refresh Control
Specifies refresh control. Selects whether refreshing is
performed for synchronous DRAM. When the refresh
function is not used, the refresh request cycle generation
timer can be used as an interval timer.
0: Refresh is not performed
1: Refresh is performed
Rev. 1.0, 02/03, page 270 of 1294