SH7760 Datasheet, PDF (889/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Data transfer cycle
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HSPI_CLK (CLKP = 0)
HSPI_CLK (CLKP = 1)
HSPI_TX
HSPI_RX
HSPI_CS
MSB 6 5 4 3 2 1 LSB
* MSB 6 5 4 3 2 1
LSB
Figure 23.4 Timing Conditions when FBS = 1
23.4.5 HSPI Software Reset
If any of the FBS, CLKP, IDIV or CLKC bit values are changed, then the HSPI software reset is
generated. The receive and transmit FIFO pointers can be initialized by the HSPI software reset.
The data transmission after the HSPI software reset should protect transmitting and receiving
protocol of HSPI, and please perform it from the first. A guarantee of operation is not offered
other than it.
While the master device is not transferring data and the HSPI is in slave mode, respecify the CS
bit to make the HSPI_CS pin the low level after the HSPI software reset.
23.4.6 Clock Polarity and Transmit Control
SPCR also allows the user to define the shift timing for transmit data and polarity. The FBS bit in
SPCR allows selection between two different transfer formats. The MSB or LSB is valid on the
falling edge of HSPI_CS. The CLKP bit in SPCR allows for control of the polarity select block
which controls which edges of HSPI_CLK shift and sample data in the master and slave.
23.4.7 Transmit and Receive Routines
The master and slave can be considered linked together as a circular shift register synchronized
with HSPI_CLK. The transmit byte from the master is replaced with the receive byte from the
slave in eight HSPI_CLK cycles. Both the transmit and receive functions are double buffered to
allow for continuous reads and writes. When FIFO mode is enabled eight entry FIFOs are
available for both transmit and receive data.
Rev. 1.0, 02/03, page 839 of 1294