SH7760 Datasheet, PDF (551/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(2) In Exit from Software Standby Mode
(a) Software standby → Interrupt
Oscillation stops
Interrupt request
WDT overflow
CKIO
STATUS
Normal ^*1
Standby ^*2
WDT count
Normal ^*1
Notes: 1. Normal : LL (STATUS1 is low and STATUS0 is low)
2. Standby : LH (STATUS1 is low and STATUS0 is high)
Figure 14.3 STATUS Output in Sequence of Software Standby → Interrupt
(b) Software standby → Power-on reset
Oscillation stops Reset
CKIO
RESET*¹
STATUS
Normal*²
Standby*³
Undefined
Reset*⁴
Normal*²
0–10 Bcyc*⁵
0–30 Bcyc*⁵
Notes:
1. When standby mode is exited by means of a power-on reset, a WDT count is not
performed. Hold RESET low for the PLL oscillation stabilization time.
2. Normal : LL (STATUS1 is low and STATUS0 is low)
3. Standby : LH (STATUS1 is low and STATUS0 is high)
4. Reset : HH (STATUS1 is high and STATUS0 is high)
5. Bcyc : Bus clock cycle
Figure 14.4 STATUS Output in Sequence of Software Standby → Power-On Reset
Rev. 1.0, 02/03, page 501 of 1294