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| SH7760 Datasheet, PDF (398/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine | |||
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CKIO
RD/FRAME
D31âD0
CSn
RD/WR
Tm1
Tmd1w
Tmd1
Tmd2
A
D0
D1
RDY
BS
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.52 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait,
32-Bit Bus Width, 64-Bit Data Transfer)
Rev. 1.0, 02/03, page 348 of 1294
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