SH7760 Datasheet, PDF (915/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial value R/W Description
1, 0

All 0
R
Reserved
These bits are always read as 0, and the write
value should always be 0.
24.2.21 GPIO Interrupt Control Register (GPIOIC)
GPIOIC is a 16-bit readable/writable register that controls interrupt inputs.
When an IRQ or IRL interrupt is used to cancel software standby mode, the standby cancellation
IRL enable bit (STBIRLEN), described in section 10.5.2 Bus Control Register 2 (BCR2), should
be set to 1.
Bit: 15 14 13 12 11 10 9
PTIR PTIR PTIR PTIR PTIR PTIR PTIR
EN15 EN14 EN13 EN12 EN11 EN10 EN9
Initial value: 0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W
8
STB
RT8
0
R/W
7
STB
RT7
0
R/W
6
STB
RT6
0
R/W
5
STB
IRQ5
0
R/W
4
STB
IRQ4
0
R/W
3
STB
IRL3
0
R/W
2
STB
IRL2
0
R/W
1
STB
IRL1
0
R/W
0
STB
IRL0
0
R/W
Bit
Bit Name Initial value R/W Description
15
PTIREN15 0
14
PTIREN14 0
13
PTIREN13 0
12
PTIREN12 0
11
PTIREN11 0
10
PTIREN10 0
9
PTIREN9 0
R/W Port Interrupt Enable
R/W The setting whether to use the port as a GPIO
R/W interrupt can be set for each bit.
R/W _{0: Uses the port as a normal I/O port}
R/W _{1: Uses the port as a GPIO interrupt}
R/W
R/W
8
STBRT8
0
7
STBRT7
0
6
STBRT6
0
R/W Standby Cancellation Setting Bit
R/W In standby mode, if an interrupt to return from
R/W standby mode is detected while the corresponding
STBRT bit is set to 1, the standby mode is
cancelled.
0: Disables canceling standby mode by detection
of an interrupt
1: Enables canceling standby mode by detection
of an interrupt
5
STBIRQ5 0
4
STBIRQ4 0
R/W Standby Cancellation IRQ Setting Bit
R/W In standby mode, if an IRQ interrupt (IRQ is in the
low level) is detected while the corresponding
STBIRQ bit is set to 1, the standby mode is
cancelled.
0: Disables canceling standby mode by detection
of an IRQ interrupt
1: Enables canceling standby mode by detection
of an IRQ interrupt
Rev. 1.0, 02/03, page 865 of 1294