SH7760 Datasheet, PDF (955/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Send_read_request
Input: RegN (address of the codec register to be read)
Disable interrupts.
Write 0 to HACRSR.STARY.
Set RegN in HACCSAR.
Wait (90ns<Wait<20µs).
Set RegN in HACCSAR.
Enable interrupts
WaitLoop_CMDAMT
Error
Yes
No
Return
Error
Get_codec_data
Clear LoopCnt2 to 0.
Input: RegN (address of the codec register to be read)
WaitLoop_RSR
Error
Yes
No
Assign HACCSAR read
value to Addr.
Error
No
Addr (R) = RegN?
Yes
Assign HACCSDR read
value to DataT.
DataT is returned.
Wait for 5 µs.
LoopCnt2 ++
No
E2 < LoopCnt 2
Yes
Error
Note: E2: Loop count required in the target system
(13<E2)
LoopCnt2: Software counter for wait insertion
Addr: Variable to hold HACCSAR read value
DataT: Variable to hold HACCSDR read value
Figure 25.6 Sample Flowchart for Off-Chip Codec Register Read (cont)
Rev. 1.0, 02/03, page 905 of 1294