SH7760 Datasheet, PDF (282/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

10.2 Input/Output Pins
Table 10.1 shows the BSC pin configuration.
Table 10.1 Pin Configuration
Name
Address bus
Data bus
Signals
A25 to A0
D31 to D0
Bus cycle start BS
Chip select 6 to 0 CS6 to CS0
Read/write
RD/WR
Row address
strobe
Read/column
address strobe/
cycle frame
RAS
RD/CASS/
FRAME
Data enable 0
WE0/
DQM0/
REG
Data enable 1
WE1/
DQM1
I/O Description
Output Address output
Input/ Data input/output
Output
Output Signal that indicates the start of a bus cycle
When setting synchronous DRAM interface or MPX
interface: asserted once for a burst transfer
For other burst transfers: asserted each data cycle
Output Chip select signals that indicate the area being
accessed
CS5 and CS6 are also used as PCMCIA CE1A and
CE1B
Output Data bus input/output direction designation signal
Also used as the DRAM/PCMCIA interface write
designation signal
Output RAS signal when setting synchronous DRAM
interface
Output Strobe signal that indicates a read cycle
When setting synchronous DRAM interface: CAS
signal
When setting MPX interface: FRAME signal
Output When setting PCMCIA interface: REG signal
When setting SRAM interface: write strobe signal for
D7 to D0
When setting synchronous DRAM interface:
selection signal for D7 to D0
Output When setting PCMCIA interface: write strobe signal
When setting SRAM interface: write strobe signal for
D15 to D8
When setting synchronous DRAM interface:
selection signal for D15 to D8
Rev. 1.0, 02/03, page 232 of 1294