SH7760 Datasheet, PDF (943/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W*² Description
9
PLTFUN 0
R/W PCML TX Underrun
0: No PCML TX underrun has occurred.
1: PCML TX underrun has occurred because the
codec has requested slot 3 with PLTFRQ = 1.
8
PRTFUN 0
R/W PCMR TX Underrun
0: No PCMR TX underrun has occurred.
1: PCMR TX underrun has occurred because the
codec has requested slot 4 with PRTFRQ = 1.
7 to 0 
All 0
R
Reserved
Always 0 for read and write.
Notes: *1 CMDAMT and CMDDMT have no associated interrupts. Poll these bits until they are
read as 1 before writing a new command to HACCSAR/HACCSDR. When bit 19 (RW)
of HACCSAR is 0 and TX12_ATOMIC is 1, take the following steps:
1. Initialize CMDDMT and CMDAMT before first accessing a codec register after HAC
initialization by any reset event.
2. After making the settings in HACCSDR and HACCSAR, poll CMDDMT and
CMDAMT until they are cleared to 1, and then initialize these bits.
3. Now the next write to a register is available.
*2 These bits are read/write. Writing 0 to the bit initializes it but writing 1 has no effect.
25.3.8 RX Interrupt Enable Register (HACRIER)
HACRIER is a 32-bit read/write register that enables or disables HAC RX interrupts.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
- ^{STAR STDR PLRF PRRF} -
-
-
YIE YIE RQIE RQIE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
PLRF PRRF
OVIE OVIE
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R R/W R/W R
R
R
R
R
R
R
R
R
R
R
R
Rev. 1.0, 02/03, page 893 of 1294