SH7760 Datasheet, PDF (1105/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

30.3.14 LCDC Vertical Sync Signal Register (LDVSYNR)
LDVSYNR specifies the vertical (scan direction and vertical direction) sync signal timing of the
LCD module.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
VSY VSY VSY VSY _- VSY VSY VSY VSY VSY VSY VSY VSY VSY VSY VSY
NW3 NW2 NW1 NW0
NP10 NP9 NP8 NP7 NP6 NP5 NP4 NP3 NP2 NP1 NP0
Initial value: 0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
R/W: R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name
Initial Value R/W Description
15
VSYNW3
0
14
VSYNW2
0
13
VSYNW1
0
12
VSYNW0
0
R/W Vertical Sync Signal Width
R/W _{Sets the width of the vertical sync signals (FLM and}
R/W _{Vsync) (unit: line).}
R/W
Specify a value of (width of vertical sync signal) −1.
Example: For a vertical sync signal width of 1 line.
VSYNW = (1−1) = 0 = H’0
11

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10
VSYNP10
0
9
VSYNP9
0
8
VSYNP8
1
7
VSYNP7
1
6
VSYNP6
1
5
VSYNP5
0
4
VSYNP4
1
3
VSYNP3
1
2
VSYNP2
1
1
VSYNP1
1
0
VSYNP0
1
R/W Vertical Sync Signal Output Position
R/W Sets the output position of the vertical sync signals
R/W (FLM and Vsync) (unit: line).
R/W _{Specify a value of (position of vertical sync signal}
R/W _{output) −2.}
R/W
R/W ^{DSTN should be set to an odd number value. It is}
R/W ^{handled as (setting value+1)/2.}
R/W _{Example: For a 480-line LCD module and a retrace}
R/W period of 0 lines (in other words, VTLN= 479 and
R/W the vertical sync signal is active for the first line):
• Single display
VSYNP = [(1−1)+VTLN]mod(VTLN+1)
= [(1−1)+479]mod(479+1)
= 479mod480 = 479 =H’1DF
• Dual address
VSYNP = [(1−1)×2+VTLN]mod(VTLN+1)
= [(1−1)×2+479]mod(479+1)
= 479mod480 = 479 =H’1DF
Rev. 1.0, 02/03, page 1055 of 1294