SH7760 Datasheet, PDF (598/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

SCIF_RXD
Serial receive
data
SPTRR
Peripheral bus
SPTRR: Read from SCSPTR
Figure 17.6 SCIF_RXD Pin
17.2 Input/Output Pins
Table 17.1 shows the SCIF pin configuration. Since the pin functions are the same in each
channel, the channel number is omitted in the description below. The modem control pins are
available only in channels 1 and 2, and not in channel 0.
Table 17.1 Pin Configuration
Pin Name
Abbreviation
I/O
Function
Serial clock pin
SCIF0_CLK to SCIF2_CLK Input/Output Clock input/output
Receive data pin
SCIF0_RXD to SCIF2_RXD Input/Output Receive data input
Transmit data pin
SCIF0_TXD to SCIF2_TXD Input/Output Transmit data output
Modem control pin SCIF1_CTS, SCIF2_CTS
Input/Output Transmission enabled
Modem control pin SCIF1_RTS, SCIF2_RTS
Input/Output Transmission request
Note: These pins are made to function as serial pins by performing SCIF operation settings with
the C/A bit in SCSMR, the TE, RE, CKE1, and CKE0 bits in SCSCR, and the MCE bit in
SCFCR. Break state transmission and detection can be set in SCSPTR of the SCIF.
Rev. 1.0, 02/03, page 548 of 1294