SH7760 Datasheet, PDF (1158/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

3. Operand access match on channel A, instruction access match on channel B
Instruction B is 0 to 3 instructions after Sequential operation is not guaranteed.
instruction A
Instruction B is 4 or more instructions Sequential operation is guaranteed.
after instruction A
4. Operand access matches on both channel A and channel B
Do not make a setting such that a single operand access will match the break conditions of
both channel A and channel B. There are no other restrictions. For example, sequential
operation is guaranteed even if two accesses within a single instruction match channel A and
channel B conditions in turn.
31.4 Usage Notes
1. Do not execute a post-execution instruction access break for the SLEEP instruction.
2. Do not make an operand access break setting between 1 and 3 instructions before a SLEEP
instruction.
3. The value of the BL bit referenced in a user break exception depends on the break setting, as
follows.
• Pre-execution instruction access break: The BL bit value before the executed instruction is
referenced.
• Post-execution instruction access break: The OR of the BL bit values before and after the
executed instruction is referenced.
• Operand access break (address/data): The BL bit value after the executed instruction is
referenced.
• In the case of an instruction that modifies the BL bit
BL bit
Pre-
Execution
Instruction
Access
0→0
A
1→0
M
0→1
A
1→1
M
A: Accepted
M: Masked
Post-
Execution
Instruction
Access
A
M
M
M
Pre-
Execution
Instruction
Access
A
M
A
M
Post-
Execution
Instruction
Access
A
M
M
M
Operand Access
(Address/Data)
A
A
M
M
Rev. 1.0, 02/03, page 1108 of 1294