SH7760 Datasheet, PDF(291/1345 Page) Renesas Technology Corp – SuperHTM RISC engine

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SH7760 Datasheet, PDF (291/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

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10.5 Register Descriptions

The BSC has the following registers. The synchronous DRAM mode register in synchronous

DRAM can be accessed as a register for this LSI. The following registers control memory

interfaces, wait-cycles, and refresh cycles, etc.

Table 10.6 Register Configuration (1)

Register Name

Abbrev. R/W

Bus control register 1

BCR1 R/W

Bus control register 2

BCR2 R/W

Bus control register 3

BCR3 R/W

Bus control register 4

BCR4 R/W

Wait control register 1

WCR1 R/W

Wait control register 2

WCR2 R/W

Wait control register 3

WCR3 R/W

Wait control register 4

WCR4 R/W

Memory control register

MCR

R/W

PCMCIA control register

PCR

R/W

Refresh timer control/status register RTCSR R/W

Refresh timer counter

RTCNT R/W

Refresh timer constant register RTCOR R/W

Refresh count register

RFCR R/W

Synchronous DRAM mode register SDMR2 W

(for area 2)

Synchronous DRAM mode register SDMR3 W

(for area 3)

P4 Address

H'FF80 0000

H'FF80 0004

H'FF80 0050

H'FE0A 00F0

H'FF80 0008

H'FF80 000C

H'FF80 0010

H'FE0A 0028

H'FF80 0014

H'FF80 0018

H'FF80 001C

H'FF80 0020

H'FF80 0024

H'FF80 0028

H'FF90 xxxx*1

Area 7 Address Size

H'1F80 0000 32

H'1F80 0004 16

H'1F80 0050 16

H'1E0A 00F0 32

H'1F80 0008 32

H'1F80 000C 32

H'1F80 0010 32

H'1E0A 0028 32

H'1F80 0014 32

H'1F80 0018 16

H'1F80 001C 16

H'1F80 0020 16

H'1F80 0024 16

H'1F80 0028 16

H'1F90 xxxx

8

Sync

Clock

Bck

Bck

Bck

Bck

Bck

Bck

Bck

Bck

Bck

Bck

Bck

Bck

Bck

Bck

Bck

H'FF94 xxxx*1 H'1F94 xxxx

8

Bck

Rev. 1.0, 02/03, page 241 of 1294

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