SH7760 Datasheet, PDF (841/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
12
IRR12
0
R/W Wake-up on Bus Activity
Indicates that a CAN bus activity is present. When
the HCAN is in sleep mode and a recessive to
dominant bit transition takes place on the CAN
bus, this bit is set. The operation of this interrupt
is configured in the Master Control Register.
(MCR7 – Auto-wake Mode). This interrupt is
cleared by writing a 1 to this bit position. Writing a
0 has no effect.
0: Bus idle state
Clearing condition: Write a 1 to this bit.
1: CAN bus activity is detected in HCAN2 sleep
mode.
Setting condition: Bit transition, from recessive
to dominant, is detected in sleep mode.
11

0
R
Reserved
This bit is always 0. Writing a 1 to this bit has no
effect. This bit is always read as 0.
10

0
R
Reserved
This bit is always. Writing a 1 to this bit has no
effect. This bit is always read as 0.
9
IRR9
0
R/W Message Overrun/Overwrite Interrupt Flag
Indicates that a message has been received but
the existing message in the matching Mailbox has
not been read due to the corresponding
CANRXPR or CANRFPR set to 1. The received
message is either abandoned (overrun) or
overwritten depeding on the value of the NMC
(New Message Control) bit. This bit is cleared by
writing a 1 to the correspondent bit position in
CANUMSR (Unread Message Status Register).
Writing a 0 has no effect.
0: No message overrun/overwrite
Clearing condition: Clean all bits in CANUMSR.
1: Receive message overrun and its storage has
been rejected or message overwrite.
Setting condition: Message is received while
the corresponding CANRXPR or CANRFPR =1
and CANMBIMR = 0.
Rev. 1.0, 02/03, page 791 of 1294