SH7760 Datasheet, PDF (658/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
Initial
Value R/W Description
4 RE
0
R/W Receive Enable
Enables/disables serial reception.
0: Disables reception*¹
1: Enables reception*²
Notes: *1. Note that clearing the RE bit to 0 has no effect
on the RDRF, PER, ERS, ORER, or WAIT_ER
flags. The state of these flags will be
maintained.
*2. If the start bit is detected in this state, serial
reception is initiated. Before setting the RE bit to
1, SISMR and SISCMR registers must always be
set, to determine the reception format.
3 WAIT_IE 0
R/W Wait Enable
Enables or disables wait error interrupt requests.
0: Disables wait error interrupt (SIMERI) requests
1: Enables wait error interrupt (SIMERI) requests
2 TEIE
0
R/W Transmit end interrupt enable
Enables or disables transmission end interrupt (SIMTEI)
requests when transmission ends and the TEND flag is set to
1.
0: Disables transmission end interrupt (SIMTEI) requests*
1: Enables transmission end interrupt (SIMTEI) requests*
Note: * After the 1 in the TDRE flag in SISSR is read, SIMTEI
can be cancelled either by writing transmit data to
SITDR and then clearing the TEND bit, or by clearing
the TEIE bit to 0.
1 CKE1
0
0 CKE0
0
R/W Clock Enable 1, 0
R/W Select the clock source for the smart card interface, and
enables or disables clock output from the SIM_CLK pin.
00: Output pin fixed at low level output
01: Output pin set for clock output
10: Output pin fixed at high level output
11: Output pin set for clock output
Rev. 1.0,02/03, page 608 of 1294