SH7760 Datasheet, PDF (16/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

16.3.5 Channels 0 to 3 Time Registers (CMTCH0T to CMTCH3T).............................. 534
16.3.6 Channels 0 to 3 Stop Time Registers (CMTCH0ST to CMTCH3ST)................. 534
16.3.7 Channels 0 to 3 Counters (CMTCH0C to CMTCH3C) ....................................... 534
16.4 Operation .......................................................................................................................... 535
16.4.1 Edge Detection..................................................................................................... 535
16.4.2 32-Bit Timer: Input Capture ................................................................................ 536
16.4.3 32-Bit Timer: Output Compare............................................................................ 537
16.4.4 16-Bit Timer: Input Capture ................................................................................ 538
16.4.5 16-Bit Timer: Output Compare............................................................................ 539
16.4.6 Counter: Up-/Updown-Counter ........................................................................... 540
16.4.7 Counter: Up-Counter with Capture...................................................................... 541
16.4.8 Interrupts.............................................................................................................. 541
16.4.9 Rotary Mode ........................................................................................................ 542
16.4.10 Timer Frequency.................................................................................................. 542
16.4.11 Standby Mode ...................................................................................................... 542
Section 17 Serial Communication Interface with FIFO (SCIF)........................543
17.1 Features............................................................................................................................. 543
17.2 Input/Output Pins .............................................................................................................. 548
17.3 Register Descriptions ........................................................................................................ 549
17.3.1 Receive Shift Register (SCRSR).......................................................................... 552
17.3.2 Receive FIFO Data Register (SCFRDR) ............................................................. 552
17.3.3 Transmit Shift Register (SCTSR) ........................................................................ 553
17.3.4 Transmit FIFO Data Register (SCFTDR) ............................................................ 553
17.3.5 Serial Mode Register (SCSMR)........................................................................... 554
17.3.6 Serial Control Register (SCSCR)......................................................................... 557
17.3.7 Serial Status Register (SCFSR)............................................................................ 560
17.3.8 Bit Rate Register (SCBRR) ................................................................................. 567
17.3.9 FIFO Control Register (SCFCR) ......................................................................... 568
17.3.10 Transmit FIFO Data Count Register (SCTFDR) ................................................. 570
17.3.11 Receive FIFO Data Count Register (SCRFDR)................................................... 570
17.3.12 Serial Port Register (SCSPTR) ............................................................................ 571
17.3.13 Line Status Register (SCLSR) ............................................................................. 574
17.3.14 Serial Error Register (SCRER) ............................................................................ 575
17.4 Operation .......................................................................................................................... 576
17.4.1 Overview.............................................................................................................. 576
17.4.2 Operation in Asynchronous Mode ....................................................................... 578
17.4.3 Operation in Synchronous Mode ......................................................................... 588
17.5 SCIF Interrupt Sources and the DMAC ............................................................................ 596
17.6 Usage Notes ...................................................................................................................... 597
Rev. 1.0, 02/03, page xiv of xlviii