SH7760 Datasheet, PDF (1070/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit Name Value R/W
11 TRGE1 0
R/W
10 TRGE0 0
R/W
9, 8 
All 0
R
7
CKSL1 0
R/W
6
CKSL0 1
R/W
5
MDS1 0
R/W
4
MDS0 0
R/W
3, 2 
All 0
R
Description
Trigger Enable
External trigger input permits or prohibits A/D conversion.
These bits must be set while conversion is stopped.
00: When an external trigger is input, A/D conversion
does not start
01: Setting prohibited
10: Setting prohibited
11: A/D conversion starts at the falling edge of an input
signal from the external trigger input pin (ADTRG)
Note: Clear bits TRGE1 and TRGE0 to 0 before
switching the trigger signal.
Reserved
These bits are always read as 0, and the write value
should always be 0.
Clock Select
These bits select the A/D conversion clock division ratio.
00: Pck/4
01: Pck/8
10: Pck/16
11: Pck/32
Note: For the Pck and clock division ratio settings, refer
to section 29.7.3, Pck and Clock Division Ratio
Settings.
Conversion Mode Select
These bits select single mode, multi mode, or scan mode.
For details on modes, see section 29.4, Operation.
The combination of MDS1 = 0 and MDS0 = 1 should not
be selected.
00: Single mode
01: Setting prohibited
10: Multi mode
11: Scan mode
Reserved
These bits are always read as 0, and the write value
should always be 0.
Rev. 1.0, 02/03, page 1020 of 1294