SH7760 Datasheet, PDF (274/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Interrupt Source
MFI
MFII
—
—
—
—
—
ADC ADI
CMT CMTI
TMU0 TUNI0
TMU1 TUNI1
TMU2 TUNI2
TICPI2
WDT ITI
REF
RCMI
ROVI
Note:
TUNI0 to TUNI2
TICPI2
ERI
RXI
TXI
SIMTEI
BRI
ITI
RCMI
ROVI
H-UDI
DMTE0 to DMTE7
DMAE
VINT
INTEVT Interrupt Priority Relevant IPR Priority within Default
Code (Initial Value) (Bit Numbers) IPR Setting Unit Priority
H'F80 15 to 0 (0)
INTPRI0C
(15 to 12)
High
H'F00 15 to 0 (0)
H'F20
INTPRI0C
(11 to 8)
High
H'F40
H'F60
Low
H'F80 15 to 0 (0)
INTPRI0C
(7 to 4)
H'FA0 15 to 0 (0)
INTPRI0C
(3 to 0)
H'400 15 to 0 (0)
IPRA (15 to 12) —
H'420 15 to 0 (0)
IPRA (11 to 8) —
H'440 15 to 0 (0)
IPRA (7 to 4) High
H'460
Low
H'560 15 to 0 (0)
IPRB (15 to 12) —
H'580 15 to 0 (0)
IPRB (11 to 8) High
H'5A0
Low
Low
: Underflow interrupts
: Input capture interrupt
: Receive-error interrupt
: Receive-data-full interrupt
: Transmit-data-empty interrupt
: Transmit-end interrupt
: Break interrupt request
: Interval timer interrupt
: Compare-match interrupt
: Refresh count overflow interrupt
: Hitachi user debug interface
: DMAC transfer end interrupts
: DMAC address error interrupt
: Vertical synchronization interrupt
Rev. 1.0, 02/03, page 224 of 1294